ps segun parece es mejor esto que lo que tiene el n95... apenas encuentre el link lo pongo...lo unico q le falta es la aceleracion 3d, pero por os y por procesador es mas rapido... porque es un 369mhz+250mhz dsp... contra 330mhz+220mhz del n95/n82, lo lei hace poco
AQUI ESTA:
What are you talking about?? Look at the N95 specs. It's a 332Mhz main processor and an auxiliar 220 Mhz, because that is an OMAP 2. It is not a dual core, it is a double processor chip set.
Don't believe it? let's go to practice! Compare multitasking or web browsing speed at the N95 and the N85/N81/N79/N78/N76/5800 or any other device with 369 Mhz processor. (I already did the test with N81, N76 and N78).
http://pdadb.net/index.php?m=cpu&id...ments_omap_2420
http://focus.ti.com/general/docs/wt...&contentId=4671
TI Home > Wireless Handset Solutions > OMAP™ Applications Processors > OMAP™ 2 Processors > OMAP2420
OMAP™ 2 Processors: OMAP2420
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OMAP2420 Processor- Availability Disclaimer
The OMAP2420 processor is a single-chip applications processor that supports all cellular standards, and complements any modem or chipset and any air interface. It is intended for high-volume wireless handset manufacturers and is not available through distributors. The OMAP2420 includes the benefits of the OMAP 2 architecture’s parallel processing, giving users the ability to instantly run applications and operate multiple functions simultaneously without quality of service compromises. The OMAP2420 includes an integrated ARM1136 processor (330 MHz), a TI TMS320C55x™DSP (220 MHz), 2D/3D graphics accelerator, imaging and video accelerator, high-performance system interconnects and industry-standard peripherals.
The so called second core is actually a DSP.
Now compare it with the so called "single processor" Freescale architecture used by most Nokias today.
http://pdadb.net/index.php?m=cpu&id...scale_mxc300-30
http://pdadb.net/index.php?m=pdamaster
http://www.freescale.com/webapp/sps...?code=MXC300-30
The MXC300-30 is the first platform with a 3G single core modem. The single core processor at the heart of the MXC300-30 combines a StarCore™ SC140e Digital Signal Processor (DSP) operating at up to 250 MHz and an ARM1136™ applications processor core operating at up to 532 MHz. The single core modem handles all the signaling protocol layers (L1, L2 and L3) for 2.5G, 2.75G and 3G standards including Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Enhanced Data for GSM Evolution (EDGE) class 12 and wideband code division multiple access (WCDMA).
# StarCore SC140 DSP up to 250 MHz
# ARM11™ applications processor up to 532 MHz"
Oh I'm sorry what's that? Internet Myth No. 2 meets actual factory documentation and gets shot down. The Freescale processor also has a secondary processor, a Digital Signal Processor. Now what's a Digital Signal Processor?
http://en.wikipedia.org/wiki/Digital_signal_processor
"A digital signal processor (DSP) is a specialized microprocessor designed specifically for digital signal processing, generally in real-time computing.
Digital signal processing algorithms typically require a large number of mathematical operations to be performed quickly on a set of data. Signals are converted from analog to digital, manipulated digitally, and then converted again to analog form, as diagrammed below. Many DSP applications have constraints on latency; that is, for the system to work, the DSP operation must be completed within some time constraint.
Architecture
* Hardware modulo addressing, allowing circular buffers to be implemented without having to constantly test for wrapping.
* A memory architecture designed for streaming data, using DMA extensively.
* Separate program and data memories (Harvard architecture)
* Special SIMD (single instruction, multiple data) operations
* Special arithmetic operations, such as fast multiply-accumulates (MACs). Many fundamental DSP algorithms, such as FIR filters or the Fast Fourier transform (FFT) depend heavily on multiply-accumulate performance.
* Bit-reversed addressing, a special addressing mode useful for calculating FFTs
* Deliberate exclusion of a memory management unit. DSPs frequently use multi-tasking operating systems, but have no support for virtual memory or memory protection. Operating systems that use virtual memory require more time for context switching among processes, which increases latency.
[edit] Program flow
* Floating-point unit integrated directly into the datapath
* Pipelined architecture
* Highly parallel multiplier–accumulators (MAC units)
* Hardware-controlled looping, to reduce or eliminate the overhead required for looping operations
[edit] Memory architecture
* DSPs often use special memory architectures that are able to fetch multiple data and/or instructions at the same time:
o Harvard architecture
o Modified von Neumann architecture
* Use of direct memory access
* Memory-address calculation unit"
Whose DSP is better?
http://www.embedded.com/design/embe...?printable=true
"Texas Instruments' TMS320C55x chip family was introduced in 2000 as a successor to the widely used TMS320C54x. The 'C55x has two MAC units (compared to one on the 'C54x and other processors in the low-cost group) and can execute up to two instructions in parallel."
"The SC140 was introduced in 1999 and, along with Texas Instruments' TMS320C62x, it was one of the early mainstream VLIW-based processors, with StarCore and TI both promoting the VLIW approach as a way to make DSP processors more compiler-friendly. The SC140 is a quad-MAC architecture that can issue and execute six instructions per cycle."
I see
Quad MAC (Multiplier Accumulators) > Dual MAC
6 Instructions parallel per cycle > 2 instructions
Bueno creo q queda claro